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Counting is frequently required in digital computers and other digital systems to record the number of events occurring in a specified interval of time. Normally an electronic counter is used for counting the number of pulses coming at the input line in a specified time period. The counter must possess memory since it has to remember its past states. As with other sequential logic circuits counters can be synchronous or asynchronous.
As the name suggests, it is a circuit which counts. The main purpose of the counter is to record the number of occurrence of some input. There are many types of counter both binary and decimal. Commonly used counters are
- Binary Ripple Counter
- Ring Counter
- BCD Counter
- Decade counter
- Up down Counter
- Frequency Counter
Binary Ripple Counter
A binary ripple counter is generally using bistable multivibrator circuits so that cache input applied to the counter causes the count to advance or decrease. A basic counter circuit is shown in Figure 1 using two triggered (T-type) flip flop stages. Each clock pulse applied to the T-input causes the stage to toggle. The Q and output terminals are always logically opposite. If the Q output is logical 1 (SET), the output is then logical 0. If the Q output is logical 0 (REST), then the output is logical 1.
The clock input causes the flip flop to toggle or change stage once clock pulse
Figure 2 (a) shows the clock input signal and Q output signal. Notice that the circuit used in this case toggles on the trailing edge of the clock signal (when logic signal goes from 1 to 0). Referring back to Figure 1 the Q output of the first stage (called the 2o stage or units position stage) is used here as the toggle input to the second stage (called the 21 or two’s position stage). The Q output from the two successive stage are marked A and B, respectively, to differentiate them. Notice that the output of each stage is marked with a negative bar over the letter designation, so that whatever logical stage A is at, is the opposite logical state.
Since the Q output (A signal) from the first stage triggers the second stage, the second stage changes state only when the Q output of first stage goes from logical 1 to logical 0 as shown in Figure 2(b).
|COUNT FOR 2-STAGE BINARY COUNTER|
|Input Pulses||2n Output (B)||2n Output (A)|
|4 or 0||0||0|
An arrow is included on the waveform of stage A as a reminder that it triggers stage B only on a trailing edge (1 or 0 logical change). Notice that the output waveform of succeeding stage operates half as fast as its input. To see that this circuit operates as a binary counter a table can be prepared to show the Q output states after each clock pulse is applied. Table 1 shows this operation for the circuit of Figure 1.
To see how a counter is made using more stage considers the 4 stage counter of Figure 3. The counter is simply made with the Q output of each state connected as the toggle input to the succeeding state. With four stages the counter cycle will repeat every sixteen clock pulses. In general there are 2n counts with an n-stage counter. For the four stages used here the count goes 24 or 16 steps as a rule, for a binary counter.
Number of counts = N = 2n
Where, n = number of counter stage. A six stage counter n = 6 would be provide a count that repeats every N = 26 = 64 counts. A ten-stage counter (n = 10) would recycle every N = 210 = 1024 counts.
Returning to the 4 stage counter Figure 3. Arrows are included in the table to act as reminder that a change from 1 to 0 results in a succeeding stage being toggled. Notice in Table 2 that the 20 stage toggles on every four clock pulses. The 21 stage toggles every two clock pulses, the 22 stage toggles every clock pulses. This implies that we can associate a weighting value to the stage output. The 23 stage output can be considered of value eight, the 22 output equal four, 21 output equals two and 20 equals one. We can see then that the binary state of the counter can be read as a number equals to the pulses input count. After the counter reaches the count 111, which is the largest count obtained using four stages, the next input pulse causes the counter to go to 000 and new count cycle repeats.
|COUNT UP OPERATION (FOUR STAGES)|
|Input Pulses||23Output (D)||22 Output (C)||21 Output (B)||20 Output (A)|
|16 or 0||0||0||0||0|
It should be obvious that the count sequence is an increasing binary count for each input clock pulse. Then the counter is also referred to as a count up binary counter the resulting output waveform for each stage is shown in Figure 4. The count is called a ripple counter because of the rippling change of state from lower order to higher order stages when the count changes i.e. the 20 stage toggles the 21 stage, which may toggle the 22 stage etc.
A simple four stage count down counter is shown is Figure 5. The Q-output of each stage is now used as trigger input to the following stage. It still use the Q-output as indication the state of each stage as shown in the count table (table 3). Starting with the counter RESET Q-output of each stage is logical-0, the first input pulse causes stage A to toggle form 0 to 1. The trigger pulse to stage B being taken from the Q-output of stage A goes from 1 to 0 at this time so that stage B is also toggled. The Q-output of stage B going from 1 to 0 causes stage C to be toggled, which then causes stage D to toggle.
Figure 5: Four Stage Count-down Binary Counter
|Input Pulse||D||C||B||A||Decimal Output Count|
|0||0||0||0||0||0 (or 16)|
|16||0||0||0||0||0 (or 16)|
Table 5 shows, then that the count goes to 1111. The next input puse toggles A. Since the signal A (used to toggle stage B) now goes input 0 to 1. Stage B and C and D remain the same, the count now being 1110. Thus, the count has deceased as a result of the input trigger pulse. In fact the count will countinue to decrease by one binary count for each input trigger pulse applied. Table 5 shows that the count will decrease to 0000 after which it will go to 1111 to repeat another count circle. Using four stage the count down counter provides a full cut off
N = 2n = 24 = 16 count
but in decreasing count mode of operation.
A decade counter is the one which goes through 10 unique combinations of outputs and then resets as the clock proceeds. We may use some sort of a feedback in a 4-bit binary counter to skip any six of the sixteen possible output states from 0000 to 1111 to get to a decade counter. A decade counter does not necessarily count from 0000 to 1001 it could count as 0000,0001, 0010, 1000, 1001, 1010, 1011, 1110, 1111, 0000, 0001 and so on.
Figure 6 shows a decade counter having a binary count that is always equivalent to the input pulse count. The circuit is essentially, a ripple counter which count up to 16. We desire however, a circuit operation in which the count advance from 0 to 9 and then reset to 0 for a new cycle. This reset is a accomplished at the desired count as follows.
- With counter REST count = 0000 the counter is ready to stage counter cycle.
- Input pulses advance counter in binary sequence up to count of a (count = 1001)
- The next count pulse advance the count to 10 count = 1010. A logic NAND gate decodes the count of 10 providing a level change at that time to trigger the one shot unit which then resets all counter stages. Thus, the pulse after the counter is at count = 9, effectively results in the counter going to count = 0.
Figure 6: Decade Counter
Table 6 provides a count table showing the binary count equivalent to the decimal count of input pulses. The table also shows that the count goes momentarily count from nine (1001) to ten (1010) before resetting to zero(0000). The NAND gate provides an output of 1 until the count reach ten. The count of ten is decoded (or sensed in this case ) by using logic inputs that are all 1 at the count of ten. When the count becomes ten the NAND gate output goes to logical 0, providing a 1 to 0 logic change to trigger the one shot unit, which then provides a short pulse to reset all counter stages.
The Q signal is used since it is normally high and goes low during the one shot timing period the flip flop in this circuit being reset by a low signal level (active low clearing). The one shot pulse need only be long enough so that slowest counter stage resets. Actually, at this time only the 21and 23 stage need be reset, but all stages are reset to insure that a new cycle at the count 0000.
The ring counter is the simplest example of a shift register. The simplest counter is called a Ring counter. The ring counter contains only one logical 1 or 0 which it circulates. The total cycle length is equal to the number of stages. The ring counter is useful in applications where count has to be recognized in order to perform some other logical operation. Since only one output is ever at logic 1 at given time extra logic gates are not required to decode the counts and the flip flop outputs may be used directly to perform the required operation.
Figure 7: Simple Ring Counter
Note that in the above diagram the Reset will reset Q2, Q3 and Q4 but will put Q1 to a logic 1 state. This 1 will circulate when clock pulses are applied.
An up down counter is a bi-directional counter and it can be made to count upwards as well as downwards. In other words an up down counter is one which can provide oth count up and down counts operations in a single unit. In the previous section it was seen that if triggering pulses are obtained from output the counter is a count up and if the triggering pulses are obtained from outputs, the counter is a count down. Figure 8 gives an up down counter. When the count up signal is high the AND gate connecting Q output and count up siganl gives and output 1 which passes through the OR gate to trigger the next flip flop. This results in the count up operation. Similarly a signal from count down line will result the circuit to act as a down counter.
Figure 8: Up Down Counter
It is a special case of a decade counter in which the counter counts 0000 to 1001 and then resets. The output weights of the flip flops in these counters are in accordance with 8421 code. For instance, at the end of seventh clock pulse, the output sequence will be 0111 (Decimal euivalent of 0111 as per 8421 code is 7). These counters will thus be different from other decade counters that provide the same count by using some kind of forced feedback to skip some of the natural binary counts Figure 9 shows a counter of the BCD type.
Figure 9: BCD Counter
Frequency counter is a digital device which can be used to measure the frequency of the periodic waveforms. The block diagram of frequency counter is shown in Figure 10.
Figure 10: Frequency Counter
A signal having time period t applied at one of the input terminal of AND gate. While a unknown signal is also applied at the other input terminal of the AND gate. Hence, it is used as a clock for counter indicates the frequency of the unknown signal in respect to this time period. The time interval of the counter may be called contents. Let us suppose that time period of gate signal is one second and unknown signal is a square wave of 250 Hertz. In this condition counter counts 250 at the end of one second. This will be frequency of unknown signal.