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Home > Electronics > Digital Electronics > Clocked or Triggered Flip Flop

Clocked or Triggered Flip Flop

A clock pulse used to operate a flip flop is illustrated in Figure 1(a). The pulse goes from a low level 0 volt, the positive logical 0 condition, to a high level ( +5 volts , the positive logic logical 1 condition going between the two logic levels at a fixed frequency rate. A clock signal as seen in Figure 1(a) has two transitions, one from low to high level the other from high to low level. For positive logic operation we define the low to high transition as the leading edge of the clock signal (Figure 1(b)) while the transition from high to low is called the clock trailing edge (Figure 1(c)).

Clock Waveform (a) Full clock Pulse (b) Leading edge (c) Trailing edge

Figure 1: Clock Waveform (a) Full Clock Pulse (b) Leading edge (c) Trailing edge

Some flip flop circuits are triggered by the clock leading edge while other units are triggered on the clock trailing edge. The particular flip flop specifications will provide this information as we shall see. Some flip flop are other logic units are triggered when the clock reaches prescribed voltage levels or goes from one voltage level to another usually without regard to voltage rise or fall time. A circuit clocked by the leading edge, as in Figure 1 (b) is referred to as being positive edge triggered while another circuit triggering on the trailing edge, as in Figure 1(c) is negative edge triggered.

Positive Edge Triggered Flip Flop

In positive edge triggered flip flops the clock samples the input line at the positive edge (rising edge or leading edge) of the clock pulse. The state of the output of the flip flop is set or reset depending upon the state of the input at positive edge of the clock. This state of the output remains for one clock cycle and the clock again samples the input line on the next positive edge of the clock. A symbolic representation for positive edge triggering has been shown in Figure 2. The arrow head at clock terminal indicates positive edge triggering. The arrow head symbol is termed as dynamic signal indicator.

Positive Edge Triggered JK Flip Flop

Figure 2: Positive Edge Triggered JK Flip Flop

Negative Edge Triggered Flip Flop

In negative edge triggered flip flops the clock samples the input lines at the negative edge (falling edge or trailing edge) of the clock pulse. The output of the flip flop is set or reset at the negative edge of the clock pulse. A symbolic representation of negative edge triggering has been shown in Figure 3. A small circle is put before the arrow head to indicate negative edge triggering.

Negative Edge Triggered JK Flip Flop

Figure 3: Negative Edge Triggered Flip Flop

Level Triggered Flip Flops

The level triggering may be of two types:

  1. Positive Triggering
  2. Negative Triggering

In the positive triggering the clock samples the input line as the clock pulse is positive, and sets/resets the flip flop according to the state of the input lines. When clock is low the outputs does not change it remains in the previous state which was at the end of the positive clock pulse. Similarly, in negative triggering the clock samples the input line as the clock is negative and sets/resets the flip flop according to the state of the input lines. When clock is high the output does not change, it remains in the previous state which was at the end of the negative clock pulse.